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1 typical on resistance, 5 v, +12 v, +5 v, and +3.3 v dual spdt switches adg1636 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features 1 typical on resistance 0.2 on resistance flatness 3.3 v to 8 v dual supply operation 3.3 v to 16 v single supply operation no v l supply required 3 v logic-compatible inputs rail-to-rail operation continuous current per channel lfcsp package: 385 ma tssop package: 238 ma 16-lead tssop and 16-lead, 4 mm 4 mm lfcsp applications communication systems medical systems audio signal routing video signal routing automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems relay replacements functional block diagrams 07983-001 adg1636 d1 d2 s2b s2a in2 in1 s1b s1a notes 1. switches shown for a logic 1 input. figure 1. 16-lead tssop 07983-002 adg1636 in1 in2 en s1b d1 s1a s2b logic d2 s2a notes 1. switches shown for a 1 input logic. figure 2. 16-lead lfcsp general description the adg1636 is a monolithic cmos device containing two independently selectable single-pole/double-throw (spdt) switches. an en input is used to enable or disable the device. when disabled, all channels are switched off. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. both switches exhibit break-before-make switching action for use in multiplexer applications. the ultralow on resistance of these switches make them ideal solutions for data acquisition and gain switching applications where low on resistance and distortion is critical. the on resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. the cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. product highlights 1. 1.6 maximum on resistance over temperature. 2. minimum distortion: thd + n = 0.007%. 3. 3 v logic-compatible digital inputs: v inh = 2.0 v, v inl = 0.8 v. 4. no v l logic power supply required. 5. ultralow power dissipation: <16 nw. 6. 16-lead tssop and 16-lead 4 mm 4 mm lfcsp.
adg1636 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v dual supply ......................................................................... 3 12 v single supply ........................................................................ 4 5 v single supply .......................................................................... 5 3.3 v single supply ........................................................................6 continuous current per channel, s or d ..................................7 absolute maximum ratings ............................................................8 esd caution...................................................................................8 pin configurations and function descriptions ............................9 typical performance characteristics ........................................... 10 test circuits ..................................................................................... 13 terminology .................................................................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 9/09rev. 0 to rev. a changes to table 4 ............................................................................ 6 1/09revision 0: initial version
adg1636 rev. a | page 3 of 16 specifications 5 v dual supply v dd = +5 v 10%, v ss = ?5 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 1 typ v s = 4.5 v, i s = ?10 ma; see figure 23 1.2 1.4 1.6 max v dd = 4.5 v, v ss = 4.5 v on resistance match between channels (?r on ) 0.04 typ v s = 4.5 v, i s = ?10 ma 0.08 0.09 0.1 max on resistance flatness (r flat(on) ) 0.2 typ v s = 4.5 v, i s = ?10 ma 0.25 0.29 0.34 max leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s (off ) 0.1 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 24 0.25 1 4 na max drain off leakage, i d (off ) 0.1 na typ v s = 4.5v, v d = ? 4.5 v; see figure 24 0.25 2 10 na max channel on leakage, i d , i s (on) 0.3 na typ v s = v d = 4.5 v; see figure 25 0.6 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 130 ns typ r l = 300 , c l = 35 pf 209 245 273 ns max v s = 2.5 v; see figure 30 t on (en) 119 ns typ r l = 300 , c l = 35 pf 148 166 176 ns max v s = 2.5 v; see figure 30 t off (en) 182 ns typ r l = 300 , c l = 35 pf 228 259 281 ns max v s = 2.5 v; see figure 30 break-before-make time delay, t d 30 ns typ r l = 300 , c l = 35 pf 17 ns min v s1 = v s2 = 2.5 v; see figure 31 charge injection 130 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise (thd + n) 0.007 % typ r l = 110 , 5 v p-p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 25 mhz typ r l = 50 , c l = 5 pf; see figure 27 c s (off ) 68 pf typ v s = 0 v, f = 1 mhz c d (off ) 127 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 220 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +5.5 v, v ss = ?5.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max v dd /v ss 3.3/8 v min/max 1 guaranteed by design, not subject to production test.
adg1636 rev. a | page 4 of 16 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 0.95 typ v s = 0 v to 10 v, i s = ?10 ma; see figure 23 1.1 1.25 1.45 max v dd = 10.8 v, v ss = 0 v on resistance match between channels (?r on ) 0.03 typ v s = 10 v, i s = ?10 ma 0.06 0.07 0.08 max on resistance flatness (r flat(on) ) 0.2 typ v s = 0 v to 10 v, i s = ?10 ma 0.23 0.27 0.32 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.1 na typ v s = 1 v/10 v, v s = 10 v/1 v; see figure 24 0.25 1 4 na max drain off leakage, i d (off ) 0.1 na typ v s = 1 v/10 v, v s = 10 v/1 v; see figure 24 0.25 2 10 na max channel on leakage, i d , i s (on) 0.3 na typ v s = v d = 1 v or 10 v; see figure 25 0.6 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 100 ns typ r l = 300 , c l = 35 pf 153 183 206 ns max v s = 8 v; see figure 30 t on (en) 80 ns typ r l = 300 , c l = 35 pf 95 103 110 ns max v s = 8 v; see figure 30 t off (en) 133 ns typ r l = 300 , c l = 35 pf 161 187 210 ns max v s = 8 v; see figure 30 break-before-make time delay, t d 25 ns typ r l = 300 , c l = 35 pf 17 ns min v s1 = v s2 = 8 v; see figure 31 charge injection 150 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise (thd + n) 0.013 % typ r l = 110 , 5 v p-p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 27 mhz typ r l = 50 , c l = 5 pf; see figure 27 c s (off ) 65 pf typ v s = 6 v, f = 1 mhz c d (off ) 120 pf typ v s = 6 v, f = 1 mhz c d , c s (on) 216 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 12 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i dd 230 a typ digital inputs = 5 v 360 a max v dd 3.3/16 v min/max 1 guaranteed by design, not subject to production test.
adg1636 rev. a | page 5 of 16 5 v single supply v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40c to +85c ?40c to 125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 1.7 typ v s = 0 v to 4.5 v, i s = ?10 ma; see figure 23 2.15 2.4 2.7 max v dd = 4.5 v, v ss = 0 v on resistance match between channels (?r on ) 0.05 typ v s = 0 v to 4.5 v, i s = ?10 ma 0.09 0.12 0.15 max on resistance flatness (r flat(on) ) 0.4 typ v s = 0 v to 4.5 v, i s = ?10 ma 0.53 0.55 0.6 max leakage currents v dd = 5.5 v, v ss = 0 v source off leakage, i s (off ) 0.05 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 24 0.25 1 4 na max drain off leakage, i d (off ) 0.05 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 24 0.25 2 10 na max channel on leakage, i d , i s (on) 0.1 na typ v s = v d = 1 v or 4.5 v; see figure 25 0.6 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 160 ns typ r l = 300 , c l = 35 pf 271 319 355 ns max v s = 2.5 v; see figure 30 t on (en) 132 ns typ r l = 300 , c l = 35 pf 172 185 201 ns max v s = 2.5 v; see figure 30 t off (en) 210 ns typ r l = 300 , c l = 35 pf 268 313 345 ns max v s = 2.5 v; see figure 30 break-before-make time delay, t d 30 ns typ r l = 300 , c l = 35 pf 17 ns min v s1 = v s2 = 2.5 v; see figure 31 charge injection 70 pc typ v s = 2.5 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 26 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 28 total harmonic distortion + noise (thd + n) 0.09 % typ r l = 110 , f = 20 hz to 20 khz, v s = 3.5 v p-p; see figure 29 ?3 db bandwidth 26 mhz typ r l = 50 , c l = 5 pf; see figure 27 c s (off ) 76 pf typ v s = 2.5 v, f = 1 mhz c d (off ) 145 pf typ v s = 2.5 v, f = 1 mhz c d , c s (on) 237 pf typ v s = 2.5 v, f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 1.0 a max v dd 3.3/16 v min/max 1 guaranteed by design, not subject to production test.
adg1636 rev. a | page 6 of 16 3.3 v single supply v dd = 3.3 v, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 3.2 3.4 3.6 typ v s = 0 v to v dd , i s = ?10 ma; see figure 23 v dd = 3.3 v, v ss = 0 v on resistance match between channels (?r on ) 0.06 0.07 0.08 typ v s = 0 v to v dd , i s = ?10 ma on resistance flatness (r flat(on) ) 1.2 1.3 1.4 typ v s = 0 v to v dd , i s = ?10 ma leakage currents v dd = 3.6 v, v ss = 0 v source off leakage, i s (off ) 0.02 na typ v s = 0.6 v/3 v, v d = 3 v/0.6 v; see figure 24 0.25 1 4 na max drain off leakage, i d (off ) 0.02 na typ v s = 0.6 v/3 v, v d = 3 v/0.6 v; see figure 24 0.25 2 10 na max channel on leakage, i d , i s (on) 0.05 na typ v s = v d = 0.6 v or 3 v; see figure 25 0.6 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 275 ns typ r l = 300 , c l = 35 pf 449 506 550 ns max v s = 1.5 v; see figure 30 t on (en) 225 ns typ r l = 300 , c l = 35 pf 306 327 338 ns max v s = 1.5 v; see figure 30 t off (en) 340 ns typ r l = 300 , c l = 35 pf 454 512 553 ns max v s = 1.5 v; see figure 30 break-before-make time delay, t d 50 ns typ r l = 300 , c l = 35 pf 28 ns min v s1 = v s2 = 1.5 v; see figure 31 charge injection 50 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 26 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 28 total harmonic distortion + noise (thd + n) 0.19 % typ r l = 33 , f = 20 hz to 20 khz, v s = 2 v p-p; see figure 29 ?3 db bandwidth 26 mhz typ r l = 50 , c l = 5 pf; see figure 27 c s (off ) 80 pf typ v s = 1.5 v, f = 1 mhz c d (off ) 153 pf typ v s = 1.5 v, f = 1 mhz c d , c s (on) 243 pf typ v s = 1.5 v, f = 1 mhz power requirements v dd = 3.6 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 1.0 a max v dd 3.3/16 v min/max 1 guaranteed by design, not subject to production test.
adg1636 rev. a | page 7 of 16 continuous current per channel, s or d table 5. parameter 25c 85c 125c unit continuous current, s or d v dd = +5 v, v ss = ?5 v tssop ( ja = 150.4c/w) 238 151 88 ma maximum lfcsp ( ja = 48.7c/w) 385 220 105 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 150.4c/w) 280 175 98 ma maximum lfcsp ( ja = 48.7c/w) 469 259 119 ma maximum v dd = 5 v, v ss = 0 v tssop ( ja = 150.4c/w) 189 126 77 ma maximum lfcsp ( ja = 48.7c/w) 301 182 98 ma maximum v dd = 3.3 v, v ss = 0 v tssop ( ja = 150.4c/w) 189 130 84 ma maximum lfcsp ( ja = 48.7c/w) 305 189 105 ma maximum
adg1636 rev. a | page 8 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. parameter rating v dd to v ss 18 v v dd to gnd ?0.3 v to +18 v v ss to gnd +0.3 v to ?18 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 850 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s or d 2 data + 15% operating temperature range industrial (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 16-lead tssop, ja thermal impedance (2-layer board) 150.4c/w 16-lead lfcsp, ja thermal impedance (4-layer board) 48.7c/w reflow soldering peak temperature, pb free 260c esd caution 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. 2 see table 5.
adg1636 rev. a | page 9 of 16 pin configurations and function descriptions nc = no connect 1 2 3 4 5 6 7 8 s1a d1 s1b nc gnd v ss in1 nc 16 15 14 13 12 11 10 9 nc en v dd s2a in2 d2 s2b nc adg1636 top view (not to scale) 0 7983-003 figure 3. 16-lead tssop pin configuration 07983-004 pin 1 indicator notes 1. nc = no connect. 2. exposed pad tied to substrate, v ss . 1 d1 2 s1b 3v ss 4 gnd 11 v dd 12 en 10 s2b 9d2 5 n c 6 i n 2 7 n c 8 s 2 a 1 5 i n 1 1 6 s 1 a 1 4 n c 1 3 n c top view (not to scale) adg1636 figure 4. 16-lead lfcsp pin configuration table 7. pin function descriptions pin no. nemonic description tssop lfcsp 1 15 in1 logic control input. 2 16 s1a source terminal. this pi n can be an input or output. 3 1 d1 drain terminal. this pi n can be an input or output. 4 2 s1b source terminal. this pi n can be an input or output. 5 3 v ss most negative power supply potential. 6 4 gnd ground (0 v) reference. 7, 8, 15, 16 5, 7, 13, 14 nc no connection. 9 6 in2 logic control input. 10 8 s2a source terminal. this pi n can be an input or output. 11 9 d2 drain terminal. this pi n can be an input or output. 12 10 s2b source terminal. this pi n can be an input or output. 13 11 v dd most positive power supply potential. 14 12 en active high digital input. when this pin is lo w, the device is disabled and all switches are off. when this pin is high, the ax lo gic inputs determine the on switches. n/a 17 (epad) ep (epad) exposed pad. tied to substrate, v ss . table 8. adg1636 tssop truth table en in sa sb 0 x off off 1 0 off on 1 1 on off table 9. adg1636 lfcsp truth table en in sa sb 0 x off off 1 0 off on 1 1 on off
adg1636 rev. a | page 10 of 16 typical performance characteristics 0.4 0.6 0.8 1.0 1.2 1.4 ?8 ?6 ?4 ?2 0 2 4 6 8 on resistance ( ? ) v s or v d voltage (v) t a = 25c v dd = +3.3v v ss = ?3.3v v dd = +5v v ss = ?5v v dd = +8v v ss = ?8v 07983-014 figure 5. on resistance as a function of v d (v s ) for dual supply 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 2 4 6 8 10 12 14 16 on resistance ( ? ) v s or v d voltage (v) v dd = 3.3v v ss = 0v v dd = 12v v ss = 0v v dd = 5v v ss = 0v v dd = 16v v ss = 0v t a = 25c 07983-015 figure 6. on resistance as a function of v d (v s ) for single supply 0.4 0.6 0.8 1.0 1.2 1.4 ?6?4?20246 on resistance ( ? ) v s or v d voltage (v) t a = +125c t a = +85c t a = +25c t a = ?40c t a = +125c t a = +85c t a = +25c t a = ?40c v dd = +5v v ss = ?5v 07983-012 figure 7. on resistance as a function of v d (v s ) for different temperatures, 5 v dual supply 0.4 0.6 0.8 1.0 1.2 1.4 024681012 on resistance ( ? ) v s or v d voltage (v) v dd = 12v v ss = 0v 07983-011 t a = +125c t a = +85c t a = +25c t a = ?40c figure 8. on resistance as a function of v d (v s ) for different temperatures, 12 v single supply 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 on resistance ( ? ) v s or v d voltage (v) t a = +125c t a = +85c t a = +25c t a = ?40c t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 5v v ss = 0v 07983-013 figure 9. on resistance as a function of v d (v s ) for different temperatures, 5 v single supply 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 on resistance ( ? ) v s or v d voltage (v) v dd = 3.3v v ss = 0v t a = ?40c t a = +25c t a = +85c t a = +125c 07983-007 figure 10. on resistance as a function of v d (v s ) for different temperatures, 3.3 v single supply
adg1636 rev. a | page 11 of 16 temperature (c) ?15 ?10 ?5 0 5 10 15 leakage current (na) 0 20406080100120 i d (off) +, ? i d , i s (on) +, + i d (off) ?, + i s (off) +, ? i s (off) ?, + i d , i s (on) ?, ? 07983-033 figure 11. leakage currents as a function of temperature, 5 v dual supply 07983-032 temperature (c) leakage current (na) 0 20406080100120 i d (off) +, ? i d , i s (on) +, + i d (off) ?, + i s (off) +, ? i s (off) ?, + i d , i s (on) ?, ? ?15 ?10 ?5 0 5 10 15 20 figure 12. leakage currents as a function of temperature, 12 v single supply ?5 0 5 10 15 20 0 20406080100120 leakage current (na) temperature (c) i d , i s (off) +, + i d , i s (off) ?, ? i d (off) ?, + i s (off) +, ? i d (off) +, ? i s (off) ?, + 07983-030 figure 13. leakage currents as a function of temperature, 5 v single supply 0 20 40 60 80 100 120 temperature (c) i d , i s (off) +, + i d , i s (off) ?, ? i d (off) ?, + i s (off) +, ? i d (off) +, ? i s (off) ?, + ?4 ?2 0 2 4 6 8 10 12 14 16 18 leakage current (na) 07983-031 figure 14. leakage currents as a function of temperature, 3.3 v single supply ?100 0 100 200 300 400 500 600 i dd ( a) 02468101214 logic (v) i dd per channel t a = 25c i dd = +12v i ss = 0v i dd = +5v i ss = ?5v i dd = +5v i ss = 0v i dd = +3.3v i ss = 0v 07983-006 figure 15. i dd vs. logic level 0 50 100 150 200 250 300 ?6 ?4 ?2 0 2 4 6 8 10 12 14 charge injection (pc) v s (v) v dd = +12v v ss = 0v v dd = +5v v ss = 0v v dd = +3.3v v ss = 0v v dd = +5v v ss = ?5v 07983-010 figure 16. charge injection vs. source voltage
adg1636 rev. a | page 12 of 16 50 100 150 200 250 300 350 400 450 ?40 ?20 0 20 40 60 80 100 120 time (ns) temperature (c) 0 7983-019 v dd = +3.3v, v ss = 0v v dd = +5v, v ss = 0v v dd = +5v, v ss = ?5v v dd = +12v, v ss = 0v figure 17. t on /t off times vs. temperature 07983-008 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ? 10 off isol a tion (db) frequency (hz) 100k 1m 10m 100m 1g 10k 1k t a = 25c v dd = +5v v ss = ?5v figure 18. off isol ation vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 crosstalk (db) frequency (hz) 100k 1m 10m 100m 1g 10k 1k 07983-018 t a = 25c v dd = +5v v ss = ?5v adjacent non-adjacent figure 19. crosstalk vs. frequency insertion loss (db) frequency (hz) 100k 1m 10m 100m 1g 10k 1k ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 t a = 25c v dd = +5v v ss = ?5v 07983-005 figure 20. on response vs. frequency ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (hz) 100k 1m 10m 10k 1k t a = 25c v dd = +5v v ss = ?5v acpsrr (db) 07983-009 no decoupling capacitors decoupling capacitors figure 21. acpsrr vs. frequency 0 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 thd + n (%) frequency (hz) 15k 20k 10k 5k 25k v dd = +3.3v v s = 2v p-p v dd = +5v v s = 3.5v p-p v dd = +5v v ss = ?5v v s = 5v p-p v dd = +12v v s = 5v p-p 07983-017 r l = 110 ? t a = 25c figure 22. thd + n vs. frequency
adg1636 rev. a | page 13 of 16 test circuits i ds sxa/sxb dx v s v 07983-020 figure 23. on resistance sxa/sxb dx v s a a v d i s (off) i d (off) 07983-021 figure 24. off leakage sxa/sxb dx a v d i d (on) nc nc = no connect 07983-022 figure 25. on leakage v out 50 ? network analyzer r l 50? inx v in sxa d x v s v dd v ss 0.1f v dd 0.1f v ss gnd 50 ? nc sxb off isolation = 20 log v out v s 07983-027 figure 26. off isolation v out 50? network analyzer r l 50? inx v in sxa d x v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? nc sxb insertion loss = 20 log v out with switch v out without switch 07983-028 figure 27. bandwidth channel-to-channel crosstalk = 20 log v out gnd sxa dx sxb v out network analyzer r l 50 ? r l 50 ? v s v s v dd v ss 0.1f v dd 0.1f v ss inx 0 7983-029 figure 28. channel-to-channel crosstalk
adg1636 rev. a | page 14 of 16 v out r s audio precision r l 110 ? inx v in sxa/sxb dx v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 0 7983-034 figure 29. thd + noise inx v out dx sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300 ? 50% 50% 90% 50% 50% 90% t on t off v in v out v in 07983-023 figure 30. switching times inx v out dx sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300? 80% t bbm t bbm v out v in 07983-024 figure 31. break-before-make time delay v in (normally closed switch) v out v in (normally open switch) off v out on q inj = c l v out inx v out dx sxa v dd v ss v dd v ss gnd c l 1nf nc sxb v in v s 0.1f 0.1f 0 7983-026 figure 32. charge injection
adg1636 rev. a | page 15 of 16 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, which is measured with reference to ground. c d (off) the off switch drain capacitance, which is measured with reference to ground. c d , c s (on) the on switch capacitance, which is measured with reference to ground. c in the digital input capacitance. t transition the delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. t on (en) the delay between applying the digital control input and the output switching on. see figure 30 . t off (en) the delay between applying the digital control input and the output switching off. see figure 30 . charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental. ac power supply rejection ratio (acpsrr) the ratio of the amplitude of signal on the output to the amplitude of the modulation. this is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p.
adg1636 rev. a | page 16 of 16 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 33. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters compliant to jedec standards mo-220-vggc. 1 0.65 bsc 0.60 max p i n 1 i n d i c a t o r 1.95 bcs 0.50 0.40 0.30 0.25 min 3.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed pa d bottom view 031006-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 34. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-13) dimensions shown in millimeters ordering guide model temperature range packag e description package option adg1636bruz 1 ?40c to +125c 16- lead thin shrink small outline package [tssop] ru-16 adg1636bruz-reel 1 ?40c to +125c 16- lead thin shrink small outline package [tssop] ru-16 ADG1636BRUZ-REEL7 1 ?40c to +125c 16- lead thin shrink small outline package [tssop] ru-16 adg1636bcpz- reel 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 adg1636bcpz-reel7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 1 z = rohs compliant part. ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07983-0-9/09(a)

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